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[VHDL-FPGA-Verilog] uart.core.for.FPGA

Description: 一个UART的FPGA core，附有详细的代码阅读笔记-A UART of the FPGA core, accompanied by a detailed code of reading notes
Platform: | Size: 614400 | Author: 获得 | Hits:

[VHDL-FPGA-Verilog] FPGA_VGA

Description: 基于FPGA的高分辨率VGA显示控制器的设计-FPGA-based high-resolution VGA display controller design
Platform: | Size: 291840 | Author: 火冰 | Hits:

[VHDL-FPGA-Verilog] VHDL-Cookbook

Description: VHDL-Cookbook 初学VHDL的好资料。-VHDL-Cookbook novice VHDL good information.
Platform: | Size: 239616 | Author: 花玉良 | Hits:

[VHDL-FPGA-Verilog] Manchester

Description: 基于FPGA/CPLD，采用VHDL语言的曼彻斯特的编解码实现。还包含曼彻斯特码的说明文档。-Based on FPGA/CPLD, using VHDL language codec Manchester realize. Manchester code also includes documentation.
Platform: | Size: 175104 | Author: 周水斌 | Hits:

[assembly language] DE2_SD_Card_Audio

Description: FPGA开发,DE2开发板上实现,从SD卡读出MP3文件并播放,(即是开发一个简单的MP3播放器)-FPGA development, DE2 development board realize, from the SD card to read out and play MP3 files, (that is, the development of a simple MP3 player)
Platform: | Size: 1291264 | Author: 朱明 | Hits:

[VHDL-FPGA-Verilog] uart

Description: 串口通讯协议，你您可以自己建个工程，再将需要的VHDL文本，添加到工程中，理解程序在仿真！-Serial communication protocol, you can build your project, and then need VHDL text, added to the project, understand the procedures in the simulation!
Platform: | Size: 10240 | Author: 张亚伟 | Hits:

[VHDL-FPGA-Verilog] ultimate_crc.tar

Description: VHDL语言实现的CRC码程序,可用于FPGA实现-VHDL language procedures realize the CRC code can be used to realize FPGA
Platform: | Size: 114688 | Author: 陈楚龙 | Hits:

[VHDL-FPGA-Verilog] spi

Description: spi协议的FPGA实现(Verlog).-spi protocol FPGA realize (Verlog).
Platform: | Size: 1024 | Author: 徐凯 | Hits:

[VHDL-FPGA-Verilog] FPGAdesignXilinx

Description: 华为内部资料，关于FPGA设计的详细过程介绍，很不错的。本文档从FPGA器件结构出发以速度路径延时大小和面积资源占用率为主题描述在FPGA设计过程中应当注意的问题和可以采用的设计技巧。-Huawei internal information, with regard to detailed FPGA design process of introduction, it is good. This document from the FPGA device structure in order to speed the path delay and area the size of the theme of the occupancy rate of resource description in the FPGA design process should pay attention to the problems and design techniques can be used.
Platform: | Size: 1705984 | Author: 高超 | Hits:

[VHDL-FPGA-Verilog] fpga_sample_program

Description: 学习vhdl硬件描述语言的一些例子的原代码，比较全面，相信对初学者很有帮助-VHDL hardware description language to learn some examples of the original code, a more comprehensive, I believe very helpful for beginners
Platform: | Size: 254976 | Author: 马斌 | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: _TENNIS 基于FPGA的乒乓球游戏硬件电路的设计与实现，有完整的 代码，并有PDF详细说明如何 VHDL - www_pudn_com.files-_TENNIS Table tennis game based on the FPGA hardware circuit design and realization of a complete code, and a detailed account of how PDF has VHDL- www_pudn_com.files
Platform: | Size: 8192 | Author: 张渊杰 | Hits:

[VHDL-FPGA-Verilog] CICFPGA

Description: 本文总结了CIC 滤波器理论要点，介绍了采用FPGA设计CIC 滤波器的基本方法，使滤波器的参数可以按实际需要任意更改，给出了仿真结，验证了设计的可靠性和可行性。采用该方法设计的CIC 滤波器已用于DDC芯片，也适合下一代高频雷达系统的要求。-This paper summarizes the main points of CIC filter theory, introduced the CIC filter design using FPGA basic ways in which filter parameters can be arbitrary according to the actual needs change, the simulation node to verify the reliability of the design and feasibility. Designed using the CIC filter has been used in DDC chips, also suitable for the next generation of high-frequency radar system requirements.
Platform: | Size: 700416 | Author: 会飞的鱼 | Hits:

[VHDL-FPGA-Verilog] i2c

Description: SAA7114 和 FPGA/CPLD之间通讯的程序，本人觉得比较好，而且里面还添加了，ROM，用来存取IIC的常数和读来的数据。-SAA7114 and FPGA/CPLD communication between the procedures, I feel better, but it also added, ROM, used to access the IIC to the constant and time data.
Platform: | Size: 8192 | Author: 张亚伟 | Hits:

[VHDL-FPGA-Verilog] FPGA

Description: FPGA培训教程，非常详细，适合初学者学习，EDA系列-FPGA training course, very detailed, suitable for beginners to learn, EDA Series
Platform: | Size: 5384192 | Author: 张蔚 | Hits:

[VHDL-FPGA-Verilog] FPGA

Description: FPGA设计全流程：Modelsim>>Synplify.Pro>>ISE 第一章 Modelsim编译Xilinx库 第二章 调用Xilinx CORE-Generator 第三章 使用Synplify.Pro综合HDL和内核 第四章 综合后的项目执行 第五章 不同类型结构的仿真-FPGA design of the whole process: Modelsim>> Synplify.Pro>> ISE Chapter ModelSim Xilinx compiler library chapter called Xilinx CORE-Generator Chapter III Synplify.Pro integrated use of Chapter IV of HDL and kernel integrated implementation of the project after the Chapter V structure of different types of simulation
Platform: | Size: 218112 | Author: 青岚之风 | Hits:

[Other] colorconv

Description: 硬件实现色彩转换功能，在FPGA处理图像时经常用到，VHDL语言。-Hardware realize color conversion function, in the FPGA image frequently used treatment, VHDL language.
Platform: | Size: 2048 | Author: BrivaMa | Hits:

[VHDL-FPGA-Verilog] mmcfpgaconfig.tar

Description: 基于FPGA的MMC卡实现，内部包含了C++仿真调试代码以及FPGA的实现代码，建立工程后可以之间编译调试-FPGA-based MMC card, Internal contains C++ Simulation debugging code, as well as the realization of FPGA code, the establishment of the project can be between the compiler debugging
Platform: | Size: 7168 | Author: 王弋妹 | Hits:

[VHDL-FPGA-Verilog] AdvancedFPGADesign

Description: 国外最新出版的高级VHDL设计指南，内容新，对从事VHDL设计的人员很有帮助，：）。-Abroad, the latest high-level VHDL design of the publication of guidelines, the contents of the new VHDL design of personnel engaged in very helpful:).
Platform: | Size: 8750080 | Author: 邢进 | Hits:

[VHDL-FPGA-Verilog] NCO_sin

Description: 基于FPGA的NCO设计,采用查表方法.八位地址线,一个周期采点256个,输出八位数据.-NCO of the FPGA-based design, using look-up table method. 8 address lines, a cycle of mining point 256, the output data 8.
Platform: | Size: 4096 | Author: wei | Hits:

[SCM] image1280-50M

Description: FPGA控制LCD屏幕显示图像，方块移动，闪烁等-FPGA control LCD screen displays images, box moving, blinking, etc.
Platform: | Size: 319488 | Author: xianchunwwang | Hits:
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